The present invention relates to structure of a read-only-memory (hereinafter referred to as ROM) which operates at high speeds and which has a high degree of integration.
In a ROM employing insulated gate field effect transistors (hereinafter referred to as MOS transistors to represent the case of using an oxide film as an insulator), a single MOS transistor is allotted to one bit of memory. Therefore, the number of elements per bit can be minimized compared to types of memories, to realize a device of a highly integrated form. Further, owing to the orderly layout of the device, design effort for LSI (large scale integration) can be reduced. Therefore, the ROM is frequently used for the logic of highly integrated microcomputers. The LSI can be realized in a highly dense integrated form featuring high-speed operation if memory cell area constituting the bits of ROM is reduced, if parasitic capacitance is reduced, and if parasitic resistance is reduced.
FIG. 1 shows the circuit structure of a major portion of a general ROM, in which reference numeral 30 denotes a memory cell array, 31 denotes memory cells consisting of MOS elements selectively formed using a mask pattern, 40 denotes data lines, and 50 denotes word lines.
FIGS. 2 and 3 are plan views showing the structures of conventional ROM memory cells. Namely, these drawings show memory cells for four bits. In the conventional structure of FIG. 2, gate electrodes 1 of MOS transistors consisting of polycrystalline silicon are connected together by aluminum lines of the first layer running in a horizontal direction to constitute word lines 2, diffusion layers are connected together by aluminum lines of the second layer running in a vertical direction to constitute ground lines 3 and data lines 4, and a thin oxide region is formed or not formed under the gate electrode 1 as represented by a hatched region 20 in FIG. 2 to write memory information. This is accomplished by changing the photomask of an isolation region 101 (usually by using LOCOS (local oxidation of silicon)). In the ROM of FIG. 2, the word lines and data lines are formed by aluminum lines having a small wiring resistance. Therefore, the delay time of the interconnection line given by the value (parasitic capacitance.times.parasitic resistance) is small, and operation can be carried out at high speeds. However, the presence of as many as five contact holes 21 in the memory of four bits makes it difficult to reduce the area of memory cells and, hence, makes it difficult to increase the degree of integration.
With the conventional structure shown in FIG. 3, on the other hand, gate electrodes of the transistors run in the horizontal direction to form word lines 5. Further, ground lines 6 and data lines 7 are formed by aluminum lines of the first layer running in the vertical direction. With the memory structure of FIG. 3, a thin oxide film is formed or not formed on a region 8 indicated by hatched lines to write information.
An insulator has been thickly formed (like in the isolation region) under the gate electrode (word line 15) in the right lower portion of FIG. 3, and information has been written already.
The structure of FIG. 3 has been disclosed in IEEE J. of SC "A 256 Kbit ROM with Serial ROM cell Structure", Roger Cuppens and L. H. M. Sevat, June, 1983, Vol. SC-18, No. 3.
In the memory cell shown in FIG. 3, the number of contact holes 22 is as small as three for the memory of four bits, and the memory cell area can be reduced compared with that of the structure of FIG. 2. However, since as many as three aluminum layers (one ground line and two data lines) are running in the vertical direction, a limitation is imposed on further reducing the area of the memory cells.
With the structure of FIG. 3, furthermore, the word lines are not straight and are long; i.e., the word lines have increased resistance and increased parasitic capacitance. Therefore, the structure of FIG. 3 is not advantageous for operating the ROM at high speed.